1. Field of the Invention
The present invention relates to an electrostatic discharge protection device of a semiconductor device (hereinafter, referred to as LSI), more particularly to an electrostatic discharge protection device which is formed in an LSI chip, and performs as a Silicon Controlled Rectifier (SCR) type operation when respective circuit devices in the LSI are protected from electrostatic discharge.
2. Description of the Prior Art
Recently, a function of an LSI has been complicated, moreover, its packaging density has been formed into high density. Further, during the fabricating process, assembling process, and others of the LSI, the LSI is liable to be easily broken because of ESD (electrostatic discharge). Therefore, an electrostatic discharge protection device (hereinafter, referred to as ESD protection device) has been used for protecting circuit devices from ESD by discharging static electricity efficiently and with a safety pass.
At the beginning of a study of ESD, a human body charge model (HBM) has stood for a breakdown mechanism caused by flowing an electric charge into LSI from an external body. A test for evaluating an electrostatic withstand amount has been performed by HBM.
Further, the breakdown mechanism of LSI due to electrostatic discharge has been explained as a phenomenon to discharge the electric charge built-up in LSI from actual detailed analysis of failure of LSI, or the electric charge electrostatically induced to an external metallic body. That is, the breakdown mechanism is explained as a charged device model (CDM). By a test corresponding to that, the electrostatic withstand amount of the ESD protection device has been evaluated and made to be an index.
A discharge current waveform of the HBM is enormously different from a discharge current waveform of the CDM. For example, a pulse rise time of the current waveform in the HBM is set as 2–10 nanoseconds (hereinafter, referred to as ns). In contrast thereto, the pulse rise time of the current waveform in the CDM is set as several hundreds picoseconds (hereinafter, referred to as ps), and a time period of the CDM is to be set extremely short period of time of approximately 1 ns. Consequently, the ESD protection device is imposed with a condition of having to operate at a very wide frequency band.
For example, a protection resistor or a diode is used for a conventional ESD protection circuit of a CMOSLSI. The conventional ESD protection circuit having these resistors and diodes, utilizes a snap-back phenomenon of a MOSFET, which has a lower resistance and an excellent performance of a voltage clamp. However, recently, in a specific application field, the above-mentioned ESD protection circuit of CMOSLSI has been replaced by such devices as a parasitic NPN bipolar junction transistor (hereinafter, referred to as NPNTr), a parasitic PNP bipolar junction transistor (hereinafter, referred to as PNPTr), a thyristor, or a silicon controlled rectifier (SCR).
In particular, in case of the CMOSLSI, a progress of fabrication of such devices has made a thickness of a gate oxide film of the MOS transistor of the CMOSLSI extremely thin. As a result, breakdown withstand voltage of the gate oxide film has been lowered, so that the gate oxide film is extremely sensitive to the electrostatic discharge. That is, a voltage when the ESD protection device is starting at a low impedance (trigger voltage) has been closely to a withstand voltage of the gate oxide film. Accordingly, it is indicated that when a large amount of discharge currents flow, a voltage exceeding an allowable limit is applied to the gate oxide film, and a danger to cause the breakdown of the gate oxide film has been enhanced. That is, for the ESD protection device, a low trigger voltage is required.
As LSI has further advanced performance, it needs to operate at higher speed. Generally, an input circuit included in a circuitry required to operate at high speed should have a reduced RC delay. In addition, when a protection circuit for protection of circuit from damage due to electrostatic charge or over-voltage application is applied to the circuitry, it increases parasitic capacitance of LSI.
The circuitry required to operate at high speed needs to suppress increase in parasitic capacitance (additional capacitance). Furthermore, to enable the circuitry to operate at high speed, a protection resistor widely used in known products and having a large resistance cannot be employed in the circuitry. That is, when having to ensure high-speed circuit operation, the circuitry subjects extremely to restriction on the protection circuit. Moreover, in terms of reduction of manufacturing cost of LSI, an area occupied on a chip by the protection circuit needs to be reduced.
A Silicon Controlled Rectifier (SCR) has been employed to address such a requirement directed to an electrostatic charge protection circuit.
U.S. Pat. No. 5,012,317 discloses a technique employing an SCR as a parasitic element and an ESD protection element to protect a CMOS integrated circuit from damage.
Based on the above-stated publication, how an SCR operates will be explained below. As shown in FIGS. 1A to 1C, the SCR disclosed in U.S. Pat. No. 5,012,317 includes: an N-type well 32 formed in a surface region of a P-type semiconductor substrate 44; and a P.sup.+ type diffusion region 1048 as an anode of the SCR and an N.sup.+ type diffusion region, both being formed in the N-type well 1032. An input pad 1012 is connected to the P.sup.+ type diffusion region 1048 and the N.sup.+ type diffusion region 50 within the N-type well 1032.
When a positive current surge is applied to the input pad 1012 connected to the SCR, the potential of the N-type well 1032 momentarily rises after a time interval on the order of about 1 nanoseconds elapses from application of the surge. When the voltage applied to the N-type well 1032 exceeds tolerable breakdown voltage (typically, 40 to 50 V) between the N-type well 1032 and the substrate, an PN junction there between is brought into an avalanche-breakdown and then an avalanche-breakdown current begins to flow into the substrate and the N-type well.
That is, the current flowing into the substrate causes to increase the potential of a region (base region) of the P-type substrate, which region is positioned below the lower surface of an PN junction between N.sup.+ type diffusion region of a lateral NPN transistor consisting of the N.sup.+ type diffusion region as a cathode, the P-type substrate and the N.sup.+ type diffusion region, and the P-type semiconductor substrate to increase, allowing current to pass through the NPN transistor.
Likewise, the current flowing into the N-type well causes the potential of a region as a base region of a PNP transistor within the N-type well, which region is positioned near the N.sup.+ type diffusion region and the P.sup.+ type diffusion region within P.sup.+ type diffusion region to decrease, allowing current to pass through the vertical PNP transistor consisting of P-type diffusion region, N-type well and P-type semiconductor substrate.
Consequently, both the NPN transistor and the PNP transistor operates so that collector currents of both transistors are increased by the positive feedback loop so as to let the SCR operate in a low resistance mode (latch-up mode), allowing the currents to flow through the SCR consequently protecting the internal circuit.
An SCR initially invented begins to protect associated circuits or components operate when an input signal exceeding the tolerable breakdown voltage between the N-type well and the substrate, and the tolerable breakdown voltage is typically so high in the range of 40 to 50 V . That is, the tolerable breakdown voltage of SCR usually exceeds that of circuits or components to be protected, resulting in difficulty in practical use of SCR. In order to address such a problem, a variety of techniques (such as a triggering technique) for making an SCR operate in a preferable mode have been proposed. For instance, U.S. Pat. No. 5,465,189 discloses a technique employing a MOS transistor to pass current through a substrate and/or an N-type well. The SCR of this type is called a low voltage triggered SCR (LVSCR).
As shown in a diagram indicating the characteristics of SCR, the trigger voltage of the low voltage triggered SCR can be lowered down to a snap back voltage at which the MOS transistor of the trigger element is snapped back (a parasitic bipolar transistor begins to operate and then enters into a low impedance mode).
A holding voltage at which the LVSCR stays operating is about 1 to 3 V, which is lower than the holding voltage, i. e., 4 to 6V, at which a typical MOS protection element stays operating. Furthermore, the dynamic resistance of the LVSCR is also far lower than that of other protection elements and in effect, the dynamic resistance of a typical LVSCR having a width of 50 micrometers is about 1 ohm. Accordingly, the LVSCR is advantageously able to keep a clamp voltage applied to elements to be protected upon injection of surge current into the elements low. As a result, when the LVSCR is employed to protect elements disposed as an input for LSI, the LVSCR is advantageously able to lower its protection resistance.
Furthermore, when the clamp voltage applied to elements to be protected is low, power consumption (the amount of heat generation during protecting operation) during operation can be kept low. It is also said that since SCR is constructed such that heat generated within an element spreads over the substrate incorporating therein the element, temperature increase due to the heat generation, which is locally confined in a protection element of MOS IC, is not confined in a local area of the substrate and therefore, the element is rarely destroyed by the thermal melt upon injection of surge current into the element.
However, as is reported in Japanese Patent Application No. 2001-85534 or the publication entitled “Breakdown and latent damage of ultra-thin gate oxide under ESD stress conditions”, the journal Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000, pp. 287–295 (2000), when discharge is completed in a very short period of time as is the case of destroy in a CDM model, overshoot voltage is large and lowers the protection performance of protection element.
This is because an NMOS transistor as a trigger element is brought into an avalanche-breakdown before SCR turns on. At this moment, the NMOS transistor should turn on to allow sufficient current to pass therethrough in order to initiate latch operation of an SCR device.
However, it takes some hundreds picoseconds to some nanoseconds for SCR to exhibit low resistance (a transition time). The transition time required for transition of SCR depends on parameters such as a base width of bipolar transistor and carrier distribution within the base thereof. In this case, when the transition time is long as compared to the rise time of surge current, SCR cannot absorb enough fraction of surge current and the trigger element has to allow almost all part of surge current to pass therethrough. However, since the trigger element has not ability to allow large current to pass therethrough (i.e., has high impedance), an overshoot voltage applied to the circuit destroys elements to be protected.
To address the aforementioned problem, elements of the circuit are correctly disposed within the circuit taking into account the geometrical region to which current flowing into the substrate should be delivered and this approach to disposing elements in correct regions is disclosed in the publication, entitled “GGSCRs: GGNMOS triggered Silicon Controlled Rectifiers for ESD Protection in Deep Submicron CMOS Process”, the journal Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2001, pp. 22–31 (2001).
In this approach, as shown in FIG. 3, the cathode of SCR is disposed between regions that are produced by dividing the cathode region for triggering. The cathode disposed therebetween is most close to the base of SCR(2), enabling efficient supply of current to the base.
Generally, SCR is unfavorably and potentially brought into a latch-up condition by noise on the system. Some publications describe a high trigger current SCR that makes trigger current extremely large.
Whether trigger current for triggering a trigger element is large or small affects an extent to which the potential of a region surrounding an anode and/or cathode is increased by the current and therefore, is determined by where the trigger element is disposed and/or how the resistance of a region close to the trigger element is ranged.
In effect, noise on system takes various forms and sometimes cannot be predicted. However, when taking into account the fact that current injected from an IO buffer adjacent to the trigger element into the substrate passes through different path than that the current generated by the trigger element passes through, whether trigger current for triggering a trigger element is large or small does not have the correlation with immunity to noise.
That is, when increasing trigger current for triggering a trigger element in a circuit configured to not control the easiness of latch-up of the circuit, the circuit faces critical risk.
The SCR clamp voltage is defined as the following in FIG. 2, such that the SCR clamp voltage is determined about 1V corresponding to 2 times forward voltage VF of diode by extrapolating the linear line on I-V curve in the TURN-ON region to the axis of abscissas. Accordingly, to ensure complete protection of elements to be protected, the SCR clamp voltage is set higher than the power supply voltage. Furthermore, since the voltage potential of the SCR is determined by the product of the current and the resistance of a path through which the current passes, when holding current holding the latch-up of SCR is made large, the desired SCR clamp voltage at the holding current can be set.
As can be seen from the equivalent circuit for SCR, it can be concluded that when highlighting resistive elements within SCR and further if SCR is configured to have a substrate and an N-type well formed in low resistance, holding current can be made high. Therefore, when the characteristics of bipolar transistor and a positional relationship between anode, cathode and edge of N-type well are previously determined, catching clearly correlation between N-type well resistance, substrate resistance and SCR clamp voltage enables achievement of desired SCR performance.
For instance, when employing a P on P.sup.+ substrate, which enables a silicon substrate to have extremely low resistance, to form SCR, adjustment of SCR (as an ESD protection element) clamp voltage is carried out in a relatively easy manner by elongating a distance between anode and cathode of SCR.
The P on P.sup.+ substrate has its substrate resistance determined only by parameters associated with a distance between a P-type well below a cathode and P.sup.+ substrate, weakly depending on other primary parameters. This is because the P on P.sup.+ substrate has substrate resistance easily determined by changing SCR structure as compared to a substrate having high resistance.
However, when employing a substrate having high resistance, potentials around the anode and cathode of SCR become significantly complicated. As can be clearly seen from the cross sectional view, when viewing a lateral bipolar element from the side of edge, next to an N-type well, of an N.sup.+ diffusion layer as a cathode, the resistance of substrate consists of a P-type well below the N.sup.+ diffusion layer and a region ranging from Shallow Trench Isolation (STI) to P.sup.+ diffusion layer as a ground electrode.
For example, when current flows to the P.sup.+ diffusion layer connected to ground potential, since typically the current flows primarily through the region near the cathode, the resistance value per unit area cannot simply produce a resistance value through computation. Moreover, since the actual length of STI is short, using the resistance determined based on STI having a long length causes a significant distortion from the correct value of a resistance to be determined. In addition, typically, SCR has a P.sup.+ guard ring in the periphery thereof for prevention of latch-up of SCR and determining accurately the substrate resistance while taking into account the resistance associated with the P.sup.+ guard ring becomes difficult.
As described above, the substrate resistance needs to be determined taking into account current distribution calculated based on the impurity profile in a direction of a depth from the surface of substrate.
Additionally, in terms of reduction of process steps and facility for the manufacture of SCR, margin of elements spaced from one another needs to be enlarged to eliminated influence of variations in the resistance value of a resistor below STI within a wafer, which variations are due to large variations in the depth of STI.
Moreover, when a difference in manufacturing conditions occurs between plants, layout pattern associated with arrangement of diffusion layers for elements needs to be changed. In this case, reticles used in the steps after completion of formation of diffusion layers need to be modified. This unfavorably forces a manufacturer to pay enormous money for modification and/or design for rework.
To avoid those problems, the techniques disclosed in U.S. Pat. No. 5,012,317 that adjusts the characteristics of SCR using an external resistor and U.S. Pat. No. 5,747,834 that adjusts the clamp voltage using a resistive element need to previously lower resistances of substrate and well so that those resistances are easily adjusted.
However, in many cases, the resistance of a substrate having large resistance cannot be lowered using normal layout method (used in the conventional technique) because of size of diffusion layer and limitation on design. For instance, when calculating the resistance of substrate based on the resistance of a resistor below an N.sup.+ diffusion layer as a cathode of SCR, the resistance of STI, and the resistance of a path ranging from a P.sup.+ diffusion layer to the bottom of STI, the resistance of substrate actually cannot be made lower than 500 ohm per 1 micrometer along SCR.
How to reduce the resistance of substrate is proposed in “High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune for IC Operation” Electrical Overstress/Electrostatic Discharge Symposium proceeding, 2002, 1A.3.1.
According to the aforementioned publication, as shown in the associated FIG. 6, the layout technique reduces the effective well (or NPN/PNP bipolar base) resistances Rpw,eff/Rnw,eff: the shorter the length of the anode and cathode stripe, LA and LC, the lower Rpw,eff/Rnw,eff respectively, the higher the SCR holding current.
A P.sup.+ diffusion layer around SCR is connected to ground potential via a polysilicon resistor of 1 to 10 ohm and adjusting the resistance of the polysilicon resistor allows holding current to be adjusted. A trigger signal for SCR is supplied from an N-type MOS transistor connected to the P.sup.+ diffusion layer.
Although a ggSCR as the aforementioned SCR for controlling holding current is configured to divide a cathode into two sub-cathodes, an HHI-SCR is configured to divide a cathode into a number of sub-cathodes to reduce the resistance of substrate.
SCR varies its performance depending not only on the resistances of substrate and well but on a distance between an anode and an N-type well and a distance between a cathode and an N-type well. Accordingly, when dividing the anode and the cathode into a number of sub-anodes and sub-cathodes, the corners of sub-anodes and sub-cathodes are rounded in the steps of exposure and etching and the profile of sub-anodes and sub-cathodes is difficult to control.
Since the dynamic resistance represents the resistance of a path along which current flows between electrodes, when effective spacing therebetween is elongated, the dynamic resistance becomes large accordingly. In addition, since speed at which SCR operates and SCR clamp voltage largely depend on the distance between a cathode and an N-type well, dividing a cathode causes many problems.
In consideration of the aforementioned problems, the present invention is directed to SCR having improved triggering performance such as low trigger voltage and high-speed triggering. In more detail, SCR includes a trigger element having lowered resistance of a path along which charges discharged by the trigger element flow and contains a number of locations within SCR through which locations trigger current is supplied.
Furthermore, in order to address the aforementioned problems observed when dividing an anode and a cathode into a number of sub-regions, the invention provides SCR configured to form a comb-shaped cathode and P.sup.+ diffusion layers for triggering are inserted into the cum of the cathode. The invention also provides SCR for supplying trigger current configured to divide SCR into fine sub-SCRs and P.sup.+ diffusion layers are inserted into the sub-SCRs. In addition to the above-described SCRs, the invention is directed to SCR, achieved by applying the invention thereto, for controlling holding current.
In the conventional SCR, the resistance of substrate and well cannot be lowered because whether or not current flowing through SCR destroys SCR depends on the number of contacts and large number of contacts are required for prevention of destroy of SCR, enlarging the area of anode and cathode. Moreover, since the resistance of substrate is determined by the resistance of a path between the lower portion of an N.sup.+ diffusion layer and a P.sup.+ diffusion layer for controlling the resistance of substrate, the invention also provides SCR having an anode within an N-type well and an N-type well contact formed in a cum-shape to reduce the resistance of N-type well.